//para los registros, A , B AluOut, Memory Data Register
module Registros(
input clk,
input reset,
input [31:0] dIn,
output reg [31:0] dOut
);

always @(posedge clk) 
        begin        
        if (!reset)
             dOut<=dIn;
        else
             dOut<=0;
        end
endmodule 
